格雷码计数器用vhdl怎样实现？

variable count:std_logic_vector(3 downto 0);
if clk'event and clk='1' then
case count is
when "0000"=>count:="0001";
when "0001"=>count:="0011";
when "0011"=>count:="0010";
when "0010"=>count:="0110";
when "0110"=>count:="0111";
when "0111"=>count:="0101";
when "0101"=>count:="0100";
when "0100"=>count:="1100";
when "1100"=>count:="1101";
when "1101"=>count:="1111";
when "1111"=>count:="1110";
when "1110"=>count:="1010";
when "1010"=>count:="1011";
when "1011"=>count:="1001";
when "1001"=>count:="1000";
when "1000"=>count:="0000";
when others=>count:="0000";
end case;
end if;

经典做法：
gray code --> general code --> gray code

自然码转格雷码
library IEEE;
use IEEE.std_logic_1164.all;

entity norm2grey is
generic (width: integer := 8);
PORT (
norm: in std_logic_vector(width - 1 downto 0);
grey: out std_logic_vector(width - 1 downto 0)
);
end norm2grey;

architecture behav of norm2grey is
begin
grey <= norm xor ('0' & norm(width - 1 downto 1));
end behav;