格雷码转自然码的VHDL实现

library IEEE;
use IEEE.std_logic_1164.all;

entity grey2norm is
generic (width: integer := 8);
PORT (
grey: in std_logic_vector(width - 1 downto 0);
norm: out std_logic_vector(width - 1 downto 0)
);
end grey2norm;

architecture behav of grey2norm is
begin
PROCESS(grey)
variable temp : std_logic;
begin
for i in width-1 downto 0 loop
temp := '0';
for j in width-1 downto i loop
temp := temp xor grey(j);
end loop;
norm(i) <= temp ;
end loop;
end PROCESS;
end behav;