在SEMICON West上, 3-D IC技术看起来仍在继续稳步前行，包括NEC电子、CEA-Leti、EV Group、SUSS MicroTec 等多家公司都发表了3-D相关的报告。
Source Link: www.semiconductor.net/article/315754-3_D_IC_Technology_Continues_to_Advance.php
NEC Electronics Corp. (Tokyo) is abandoning plans to use doped polysilicon as the conductor for DRAM TSVs, and will move to metal-filled structures, according to Hiro Nakajima, senior manager of NEC's packaging engineering division. NEC changed its plans because with poly there were "difficulties in making consistent ohmic contact to the backside of the TSVs," Nakajima said at the SEMICON West Packaging Summit. Nakajima revealed that NEC has switched to plated nickel as the conductor, rather than copper or tungsten. NEC decided against copper because of "DRAM contamination issues," and Nakajima said tungsten would require costly chemical vapor deposition (CVD) equipment, which memory products could not afford.
CEA-Leti (Grenoble, France) is stepping up its 3-D related efforts. Nicolas Sillon, group manager for packaging and integration technologies, and André Rouzaud, vice president of the heterogeneous integration division, said a full 300 mm 3-D line will be running at Leti by 2010. An EV Group bonder/debonder is being installed this summer and an STS etcher and Semitool plating line will be arriving in the fall. With the already announced 300 mm lines at IMEC and Fraunhofer IZM-Dresden, the addition of the Leti line will result in three 300 mm 3-D development lines in place in Europe.
EV Group (EVG, St. Florian, Austria) announced a joint effort with Applied Materials Inc. (Santa Clara, Calif.) to develop wafer-bonding processes for the manufacture of through-silicon vias (TSVs) in 3-D IC packaging applications. The two companies will be working together as members of the EMC3D semiconductor equipment and materials consortium. The collaboration will explore the use of silicon and glass carrier wafers to determine substrate stability using EVG's wafer bonding and thin-wafer handling expertise, and Applied's advanced etch, CVD, PVD and CMP systems.
The goal of the joint effort is to yield baseline processes and recommendations for the use of carrier-mounted wafers throughout the individual process steps offered by both parties. Results from the partnership will be shared with EMC3D member companies. Applied previously announced similar agreements with Semitool (Kalispell, Mont.) and Disco Corp. (Tokyo).
Speaking at a SUSS MicroTec (Garching, Germany) workshop on thin wafer processing for 3-D TSV applications, Scott Sullivan, chief technologist at Disco, said his company has one current customer that is grinding and polishing wafers down to 8 μm in total thickness. Chris Milasincic, business development manager for HD MicroSystems, a joint venture between Hitachi Chemical and DuPont, described a new series of high-temperature polyimide-based adhesives for both temporary (HD3007) and permanent (HD7002) wafer bonding. Used in combination, these adhesives can eliminate the need for thin-wafer handling, he said.
