ST公司的STi5197是低成本QAM解调器和MPEG2译码器, 标准清晰度(SD) STB系统级芯片( SoC). STi5197集成了QAM解调器,音频/视频译码,视频处理,图像和显示,先进的安全性,STB外设,音频/视频DAC,数字音频/视频输出,USB 2.0主控制器/UPI以及以太网MAC MII/RMII,形成完整的STB解决方案,非常适合于基于MPEG2的线缆网络应用.本文介绍了STi5197的主要特性,方框图以及多种应用框图包括MPEG2广播有线STB方框图, 双调谐混合/DVR有线STB方框图,以及MPEG2交互式有线STB方框图.

Low-cost QAM demodulator and MPEG2 decoder for set-top box applications

The STi5197 uses state of the art process technology to provide an ultra low cost, full

featured, SD set-top box SOC. It is a highly integrated solution combining QAM

demodulation, audio/video decoding and applications processing into a single chip, suitable for MPEG2 based Cable networks worldwide.

The STi5197 provides a solution for operators to specify a range of low cost SD STBs

including low cost Zappers, Interactive STBs and DVR-capable STBs, with content delivery using broadcast or broadband networks, or both (Hybrid STBs).

The STi5197 is optimized for secure Pay-TV applications with integrated DVB, DES, Multi2 and ICAM descramblers and Smart Card interfaces. It also has advanced security features normally found in mid-to-high end devices to further safeguard operator and content investment.

The STi5197 offers enhancements in performance, features and integration to current users of ST’s MPEG2 SD family of audio/video decoders and QAM demodulators, whilst reducing cost and time-to-market for the next generation of deployments. Few external components are required to realize a complete STB solution, resulting in very low BOM cost.

STi5197主要特性:

The STi5197 integrates in a single IC, QAM demodulation, FEC, Multi-stream transport

demux, applications CPU, audio/video decode, video processing, graphics and display,

advanced security, STB peripherals, audio/video DACs, digital audio/video outputs, USB 2.0 host controller/ULPI and Ethernet MAC MII/RMII.

QAM demodulator/FEC

– High-performance 12-bit A/D converter suitable for direct IF architecture in all QAM (quadrature amplitude modulation) modes

– Demodulation and decoding of ITU-T J.83-Annexes A/B/C and DVB-C bit streams

– Full digital demodulation

– Variable symbol rates

– Supports 16, 32, 64, 128 and 256 point constellations

– Front derotator for better low symbol rate performance and relaxed tuner constraints

– Integrated matched filtering

– Robust integrated adaptive pre and post equalizer

– On-chip Forward Error Correction (FEC) supporting Annexes A, B and C, with ability to bypass individual blocks

– Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs)

– Integrated signal quality monitors, plus lock indicator

– Processes Japanese transport stream multiplex frame (TSMF)

High performance CPU for applications, middleware, drivers, audio decoding and network protocols

– ST40-300, dual-issue, applications CPU

– FPU, MMU, 32KI, 32KD 2-way set associative caches

– Supports OS21 and Linux operating systems

– Target speed > 350 MHz delivering >580DMIPs

Single, 16-bit wide, unified local memory interface

– Supports both SDR SDRAM up to 166 MHz and DDR1 SDRAM up to 200 MHz

MPEG2 MP@ML video decoder, dual SD decoding/PIP capable

Audio sub-system

– MPEG-1 layers I/II decoding

– MP3 decoding

– Dolby Digital 5.1 decoding and down mix to Stereo/Pro-logic

– Concurrent decoding of audio description

– Optional feature: BTSC stereo encoding

– PCM mixing with sample rate conversion

– Simultaneous audio decode and output of Dolby streams on S/PDIF

IEC60958/IEC61937 digital audio output interface

– Integrated stereo audio DAC system

Programmable external memory interface

– Four separately configurable banks, 8/16-bits wide

– SRAM, peripheral, NOR Flash, NAND Flash, Burst Mode Flash support

– Boot from NOR or NAND Flash

– Support for DVB-CI module host interface

– Fast synchronous MPX (master) protocol on EMI for interface to STv0498 Triple

QAM/DOCSIS cable modem IC

Interface to, and boot from, Serial FLASH via high speed SPI interface

– High speed Dual I/O support

Graphics/Display processing

– High performance 2-D graphics blitter accelerator and display compositor, Link list

control

– Multi-plane video/graphics composition with alpha blending, typical four-plane use

case (background color + still plane + video plane + OSD plane), and integrated

Tile RAM bandwidth saver for enhanced performance

– High quality horizontal and vertical reformatting and resizing, with sample rate

conversion/filtering for video and graphics

– 8 bpp CLUT and 16 bpp true color graphics formats supported

– Advanced anti-flicker filtering

– De-interlacing SD to 480p/576p for HDMI output

Display output

– PAL/NTSC/SECAM encoder

– Encoding of CGMS, Teletext, WSS, VPS, Closed caption

– Macrovision 7.1D copy protection

– Four 10-bit video DACs, outputting RGB/CVBS/YC analog video signals

– High drive-capability on one of the video DACs for CVBS output without buffering

– 8-bit digital video output (DVO), compliant with ITU-R BT 601/656 formats

– 54 MHz output data rate on DVO supporting 480p/576p output over 8 bits

DVR capable transport sub-system

– TS reception from internal QAM demodulator

– External TS interface for a second stream input from external tuner/demodulator

– Dual internal TS from memory for network/IP stream input and DVR playback

– TS output for routing to DVB-CI module

– DVB-compliant, triple-stream transport de-multiplexing

DVB, DES, Multi2 descrambling

ICAM2.2 NDS Conditional Access

DVR supported with HDD attachment via EIDE (PIO mode) or USB 2.0

Multi-channel flexible DMA Controller

Connectivity

– 10/100 Ethernet MAC with MII/RMII interface to external PHY

– USB 2.0 Host Controller with ULPI interface to external PHY

On-Chip STB Peripherals

– Two Smart Card Interfaces with integrated clock generation

– Four UARTs with Tx and Rx FIFOs

– Three SSCs for I²C/SPI master/slave interfaces, one of which can be dedicated for

tuner control with minimum tuner disturbance

– Five 8-bit GPIO banks with alternate functions

– Infrared transmitter/receiver

– PWM

– CEC line controller

System services

– All clocks generated from a single external crystal

– Integrated DCO for clock recovery

– Low power/RTC/watchdog controller

– JTAG/TAP interface

Advanced security

– Secure control words

– Code authentication

– JTAG interface locking

– DVR copy protection

On chip 1V (nominal) voltage regulator

Two package options

– 23mm x 23mm. Full Specification, with EMI

– 15mm x 15mm. Full Specification, except no EMI and boot from Serial FLASH

Only



图1. STi5197方框图



图2.STi5197 MPEG2广播有线STB方框图



图3.STi5197 带HDD MPEG2双调谐混合/DVR有线STB方框图



图4.STi5197 带DVB-CI插座的MPEG2广播有线STB方框图



图5.STi5197 嵌入DOCSIS有线调制解调器的MPEG2交互式有线STB方框图