ADI 公司的AD9268是双路16位125MSPS ADC,支持低成本小型化的通信应用.双ADC核具有多级流水线架构,并集成了输出误差修正逻辑.每个ADC具有宽带差分取样保持模拟输入放大器,支持各种用户可选择的输入范围,并集成了基准电压源. AD9268工作电压1.8V,125MSPS时功耗为675mW,SNR为77.3dBc(到70MHz),SFDR为88dBc(到70MH z),IF取样频率高达250MHz,可广泛应用在通信,各种无线电系统,多模式数字接收器(GSM, EDGE, WCDMA, LTE,CDMA2000, WiMAX, TD-SCDMA0,I/Q解调系统,智能天线系统,通用软件无线电,以及宽带数据和超声设备等.本文介绍了AD9268的主要特性格,产品亮点和功能方框图以及评估板详细电路图. AD9268: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Dual ADC The AD9268 is a dual, 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either1.8 V CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of 40℃ to +85℃. AD9268 主要特性: SNR = 77.3 dBc (78.3 dBFS) to 70 MHz 125 MSPS SFDR = 88 dBc to 70 MHz 125 MSPS (w/o dither) Low power: 675 mW 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 250 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 450 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes AD9268 应用: Communications Diversity radio systems Multimode digital receivers (3G) GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound Equipment AD9268 亮点: 1. On-chip dither option for improved SFDR performance with low power analog input. 2. Integrated dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS ADC. 3. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz. 4. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. 5. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. 6. Pin compatibility with the AD9258 allowing a simple migration from 16 bits to 14 bits.  图1.AD9268 功能方框图  图2.AD9268 评估板电路图(1)  图3.AD9268 评估板电路图(2)  图4.AD9268 评估板电路图(3)  图5.AD9268 评估板电路图(4)  图6.AD9268 评估板电路图(5)  图7.AD9268 评估板电路图(6)  图8.AD9268 评估板电路图(7)  图9.AD9268 评估板电路图(8)  图10.AD9268 评估板电路图(9) |
