TI 公司的UC1825是PWM控制器件,非常适合高频开关电源应用. UC1825的特别之处是通过比较器和逻辑电路最小化传输时延,同时最大化误差放大器的带宽和转换速率. UC1825的开关频率高达1MHz,50ns传输时延至输出,符合QML-V认证和 SMD 5962-87681以及Rad容差为 30 kRad (Si) TID. UC1825具有大电流双图腾柱输出,峰值电流1.5A,起动电流仅为1.1mA,逐个脉冲进行限流,软起动/最大占空比控制和带滞后的欠压锁住.本文介绍了UC1825的主要特性, 方框图以及采用UC1835的50W设计案例.

    The UC1825 PWM control device is optimized for high-frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either current-mode or voltage mode systems with the capability for input voltage feed-forward.

    Protection circuitry includes a current limit comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty-cycle clamp. The logic is fully latched to provide jitter-free operation and prohibit multiple pulses at an output. An undervoltage lockout section with 800 mV of hysteresis assures low start up current. During undervoltage lockout, the outputs are high impedance.

    This device features totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is designed as a high level.

    UC1825主要特性:

    QML-V Qualified, SMD 5962-87681

    Rad-Tolerant: 30 kRad (Si) TID(1)

    Compatible With Voltage- or Current-Mode Topologies

    Practical Operation Switching Frequencies to 1 MHz

    50-ns Propagation Delay-to-Output

    High-Current Dual Totem Pole Outputs (1.5 A Peak)

    Wide Bandwidth Error Amplifier

    Fully Latched Logic With Double-Pulse Suppression

    Pulse-by-Pulse Current Limiting

    Soft Start/Maximum Duty-Cycle Control

    Undervoltage Lockout With Hysteresis

    Low Start-Up Current (1.1 mA)

图1.UC1825方框图

图2.UC1825开环实验室测试电路

图3.采用UC1835的设计案例: 50 W, 48V到5V DC/DC 转换器 – 1.5-MHz时钟频率