module div_5 (clk_in, clk_out, reset);
input clk_in, reset;
output clk_out;
reg[2:0] gare;
reg clk_out;

initial
begin
gare = 4;
clk_out = 0;
end
always @ (clk_in)
begin if(!reset) clk_out = 0;
else
if (gare == 0)
begin
clk_out = ~clk_out;
gare = 4;
end
else gare = gare -1;
end
endmodule